1. Field of this Invention
This disclosure relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device using a voltage higher than a power supply voltage.
2. Description of the Related Art
Generally, a semiconductor integrated circuit device performs an internal operation by means of an externally provided power supply voltage. In addition, the semiconductor integrated circuit device internally generates a higher voltage than the externally provided power supply voltage and performs an internal operation using the higher voltage. In a semiconductor memory device that uses a voltage of 3.3V or greater, a MOS transistor of a circuit region driven with the power supply voltage (hereinafter, referred to as a low-voltage circuit region) has a breakdown voltage capable of enduring the internally generated higher voltage, for example, in a semiconductor integrated circuit device that uses a voltage of 3.3V or greater. In this case, a circuit region operating at a high voltage (hereinafter, referred to as a high-voltage circuit region) may be directly connected to the low-voltage circuit region. Even if the high-voltage circuit region is directly connected to the low-voltage circuit region, the MOS transistor of the low-voltage circuit region may not be broken down by the high voltage from the high-voltage circuit region. This is because the MOS transistor of the low-voltage circuit region has a breakdown voltage capable of enduring the high voltage.
As power supply voltages become lower and the increased integration of semiconductor integrated circuit device accelerates, a low-voltage transistor whose current capacity is large and whose size is small is used as the MOS transistor in the low-voltage circuit region. Therefore, the breakdown voltages of the low-voltage circuit region are also lowered. Especially if the breakdown voltage of the low-voltage transistor is lower than the high voltage used in the high-voltage circuit region, the low-voltage transistor of the low-voltage circuit region may break down due to the high voltage from the high-voltage circuit region, which is supplied when the low-voltage circuit region is directly connected to the high-voltage circuit region.
FIG. 1 is a block diagram illustrating a conventional high-voltage generator circuit. The high-voltage generator circuit 100 in FIG. 1 is disclosed in U.S. Pat. No. 5,276,646, entitled “HIGH VOLTAGE GENERATING CIRCUIT FOR A SEMICONDUCTOR MEMORY CIRCUIT”, which is herein incorporated by reference.
Referring to FIG. 1, the high-voltage generator circuit 100 includes a high-voltage pump block 110 and a voltage detector block 120. The high-voltage pump block 110 generates a high voltage Vpp in response to a pump control signal PUMP_OSC, and the high voltage Vpp is provided to a peripheral circuit and the voltage detector block 120. The pump control signal PUMP_OSC is a clock signal of a predetermined period. The voltage detector block 120 determine whether the high voltage Vpp reaches a target voltage, and generates a pump control signal PUMP_OSC as a detection result. For example, if the high voltage Vpp is lower than the target voltage, the voltage detector block 120 generates a pump control signal PUMP_OSC that oscillates in a predetermined period. The high-voltage pump block 110 performs a pump operation in response to the pump control signal PUMP_OSC, and the high voltage may increase to a target voltage as a result. When the high voltage Vpp reaches the target voltage, the voltage detector block 120 inactivates the pump control signal PUMP_OSC. This makes the high-voltage pump block 110 not operate anymore. Therefore, the high voltage Vpp is maintained uniformly.
FIG. 2 is a circuit diagram illustrating the voltage detector block 120 of FIG. 1. Referring to FIG. 2, the voltage detector block 120 includes a voltage divider 121, a comparator 122, a pump control signal generator 123, a discharge section 124, and inverters INV3 and INV4. The voltage divider 121 comprises resistors R1 and R2 and an NMOS transistor MN1, and divides a high voltage Vpp to generate a divided voltage Vdiv according to a resistance ratio of the resistors R1 and R2. The comparator 122 includes PMOS transistors MP1, MP2, and MP3 as well as NMOS transistors MN2, MN3, and MN4. The comparator compares the divided voltage Vdiv with a reference voltage Vref. The pump control signal generator 123 includes NAND gates G1 and G2 and inverters INV1 and INV2. The signal generator 123 generates a pump control signal PUMP_OSC in response to an output of comparator 122, control signal C2 through inverters INV3 and INV4, and an oscillation signal OSC. A discharge section 124 includes a PMOS transistor MP4 and NMOS transistors MN5 and MN6. The discharge section 124 discharges the high voltage Vpp to a power supply voltage in response to outputs /C2 and C2 of the inverters INV3 and INV4.
In FIG. 2, the NMOS transistors MN5 and MN6 are high-voltage transistors each having a breakdown voltage capable of enduring the high voltage Vpp, and the remaining transistors are low-voltage transistors having a relatively low breakdown voltage compared to the high-voltage transistors MN5 and MN6.
FIG. 3 is a timing diagram illustrating the operation of the high-voltage generator circuit of FIG. 1.
Referring to FIGS. 2 and 3, control signals C1 and C2 become high and an oscillation signal OSC is provided from an oscillation circuit (not shown) to the high-voltage generator circuit 100. A pump control signal generator 123 generates a pump control signal PUMP_OSC in synchronization with the oscillation signal OSC because the control signal C2 is at a high level and the divided voltage Vdiv is lower than a reference voltage Vref (e.g., 0.8V) at an initial pump operation or before the high-voltage Vpp reaches a target voltage. The high-voltage pump block 110 performs a pump operation in response to the pump control signal PUMP_OSC oscillating in a given period, and as a result, the high voltage Vpp increases toward the target voltage. If the high voltage Vpp reaches the target voltage, the comparator 122 generates a low-level signal. Because the low-level signal as an output of the comparator 122 and an output (i.e., a high-level signal) of the inverter INV4 are applied to the NAND gate G1, the pump control signal generator 123 generates the pump control signal PUMP_OSC of a low level regardless of the oscillation signal OSC. This means that the high-voltage pump block 110 does not operate. If the high voltage Vpp is lowered by an internal operation, the voltage detector block 120 generates the pump control signal PUMP_OSC oscillating in the given period, thus increasing the lowered high voltage Vpp to the target voltage.
When the desired internal operation is ended, each of the control signals C1 and C2 transitions from a high level to a low level as illustrated in FIG. 3. When the control signal C1 transitions to the low level, the NMOS transistor MN1 is turned off. At the same time, when the control signal C2 transitions to a low level, the transistors MP4 and MN5 of the discharge section 124 are turned on by outputs of the inverters INV3 and INV4. As the transistors MP4 and MN5 are turned on, the high voltage Vpp is discharged to a power supply voltage through transistors MN6, MN5, and MP4.
When the control signals C1 and C2 are all at a high level, only a low voltage (e.g., the voltage is the same as the reference voltage or lower) is applied to a node ND1. However, when all of the control signals C1 and C2 become low to discharge the high voltage Vpp, the high voltage Vpp is applied to the node ND1 in an instant. Since the high voltage of the node ND1 is applied to a drain of the NMOS transistor and a gate of the NMOS transistor MN3, the NMOS transistors MN1 and MN3 are broken down. Thus, the NMOS transistors MN1 and MN3 of the high-voltage generator circuit break down when the high voltage Vpp is discharged.
Embodiments of the invention address these and other disadvantages of the conventional art.